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| ACTS20MS April 1995 Radiation Hardened Dual 4-Input NAND Gate Pinouts 14 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T14, LEAD FINISH C TOP VIEW A1 1 B1 2 NC 3 C1 4 D1 5 Y1 6 GND 7 14 VCC 13 D2 12 C2 11 NC 10 B2 9 A2 8 Y2 Features * 1.25 Micron Radiation Hardened SOS CMOS * Total Dose 300K RAD (Si) * Single Event Upset (SEU) Immunity <1 x 10-10 Errors/Bit-Day (Typ) * SEU LET Threshold >80 MEV-cm2/mg * Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse * Latch-Up Free Under Any Conditions * Military Temperature Range: -55oC to +125oC * Significant Power Reduction Compared to ALSTTL Logic * DC Operating Voltage Range: 4.5V to 5.5V * Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2V Min * Input Current 1A at VOL, VOH 14 LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR, CDFP3-F14, LEAD FINISH C TOP VIEW A1 B1 NC C1 D1 Y1 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC D2 C2 NC B2 A2 Y2 Description The Intersil ACTS20MS is a radiation hardened dual 4-input NAND gate. A low on any input forces the output to a high logic state. The ACTS20MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family. Ordering Information PART NUMBER ACTS20DMSR ACTS20KMSR ACTS20D/Sample ACTS20K/Sample ACTS20HMSR TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC +25oC +25oC +25oC SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 14 Lead SBDIP 14 Lead Ceramic Flatpack 14 Lead SBDIP 14 Lead Ceramic Flatpack Die Truth Table INPUTS An L X X X H Bn X L X X H Cn X X L X H Dn X X X L H OUTPUT Yn H H H H L Functional Diagram (1, 9) An Bn (2, 10) (6, 8) Yn (4, 12) Cn Dn (5, 13) NOTE: L = Logic Level Low, H = Logic level High, X = Don't Care CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 Spec Number 1 518824 File Number 3611 |
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